The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device including a plurality of MIS transistors.
Recently, a static random access memory (SRAM) is used as a high-speed memory device. In particular, since it is necessary to simultaneously execute a read operation and a write operation in speech processing and image processing, an SRAM with a two-port structure (hereinafter referred to as a “two-port SRAM”) is used (see, for example, Japanese Laid-Open Patent Publication No. 2003-297953).
Now, a conventional semiconductor device including a two-port SRAM will be described with reference to the accompanying drawing. FIG. 7 is a schematic plan view of the conventional semiconductor device including the two-port SRAM.
It is noted that semiconductor regions and gate electrodes are shown with contacts, lines and the like omitted in this drawing.
As shown in FIG. 7, the conventional two-port SRAM has a structure in which an SRAM cell Mem1 and an SRAM cell Mem2 each corresponding to one bit are adjacent to each other with a boundary of line A-A. Transistors of the SRAM cell Mem1 and the SRAM cell Mem2 are axisymmetrically disposed about line A-A.
The SRAM cell Mem1 includes four access transistors TrA1, TrA2, TrA3 and TfA4 of N-type MIS transistors, two driver transistors TrD1 and TrD2 of N-type MIS transistors and two load transistors TrL1 and TrL2 of P-type MIS transistors.
Next, the specific arrangement of the transistors in the SRAM cell Mem1 will be described. The SRAM cell Mem1 has semiconductor regions RP1, RP2, RP3, RP4, RN1 and RN2. The semiconductor regions RP1, RP2, RP3, RP4, RN1 and RN2 are surrounded by an isolation region STI to be separated from one another.
A first gate line G1 is formed on the first semiconductor region RP1. The first gate line G1 extends onto the second semiconductor region RP2. A portion of the first gate line G1 disposed on the first semiconductor region RP1 works as a gate electrode of the first access transistor TrA1 and a portion thereof disposed on the second semiconductor region RP2 works as a gate electrode of the second access transistor TrA2.
A second gate line G2 is formed on the third semiconductor region RP3. The second gate line G2 extends onto the fourth semiconductor region RP4. A portion of the second gate line G2 disposed on the third semiconductor region RP3 works as a gate electrode of the third access transistor TrA3 and a portion thereof disposed on the fourth semiconductor region RP4 works as a gate electrode of the fourth access transistor TrA4.
A third gate line G3 is formed on the second semiconductor region RP2. A portion of the third gate line G3 disposed on the second semiconductor region RP2 works as a gate electrode of the first driver transistor TrD1. On the other hand, a fourth gate line G4 is formed on the fourth semiconductor region RP4. A portion of the fourth gate line G4 disposed on the fourth semiconductor region RP4 works as a gate electrode of the second driver transistor TrD2.
The third gate line G3 extends onto the fifth semiconductor region RN1. A portion of the third gate line G3 disposed on the fifth semiconductor region RN1 works as a gate electrode of the first load transistor TrL1. On the other hand, the fourth gate line G4 extends onto the sixth semiconductor region RN2. A portion of the fourth gate line G4 disposed on the sixth semiconductor region RN2 works as a gate electrode of the second load transistor TrL2.
In the two-port SRAM, the first access transistor TrA1 and the second access transistor TrA2 should have the same transistor characteristics.
In accordance with refinement of semiconductor devices, however, it is difficult to form the first access transistor TrA1 and the second access transistor TrA2 with the same transistor characteristics, and there arises a problem that a difference in the transistor characteristics is large.
A write margin of an SRAM has positive correlation with a ratio in the saturation current value of a load transistor to an access transistor. Therefore, for example, in the case where the saturation current value of the first access transistor TrA1 is smaller than the saturation current value of the second access transistor TrA2, there arises a problem that a write margin obtained in using the first access transistor TrA1 is smaller than that obtained in using the second access transistor TrA2.
Such a problem occurs not only in an SRAM but also in any semiconductor device including a plurality of transistors whose characteristics should be equivalent.